Zenith Z-100 Series Uživatelský manuál stáhnout pdf

Z-100 LifeLine IDE Interface and NVsRAM Board Design Description

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Z100 IDE Interface and NVSRAM Board Design

Description – Large Scale Design 3.0

By Charles Hett, Lenexa Kansas

Introduction

The Z-100 LifeLine IDE Interface and NVSRAM

design, hereafter referred to as the Z100 IDE

Interface is a multifunction S-100 board designed

for the Heath/Zenith Z-100 Series computer. It

provides the following features:

• An interface from the Z-100 S-100

computer bus to the industry standard IDE

hard drive interface. This allows you to

connect to up to four standard IDE drives

which are now much more available than

the old MFM hard drives originally

supported on the Z-100. DMA

capabilities, however, are not supported.

Solid state memory devices, such as

compact flash cards, that use the IDE

interface are also usable.

The circuit design described here utilizes a

complex programmable logic device

(CPLD) from Altera for all of the control

circuitry.

Design Note: This programmable device

was chosen because it would make

development easier and the design

hopefully more reliable and require less

power. Altera was chosen because the

development tools were readily available

from their web site.

• A bootable NVsRAM device. This

nonvolatile memory storage device, based

on the Texas Instruments bq4850

programmable NVsRAM, can be

programmed at any time without removing

it from the board. The NVsRAM device is

fully bootable and can contain up to 512k

of user selectable programs or files,

making it an excellent choice for holding

the Z-DOS bootup files. The bq4850 has

an onboard real time clock and an internal

battery for memory retention. Therefore, no

special programming voltage is required and

programming is greatly simplified with no

special timing routines required. Other

models are available; see the schematic for a

listing of devices thought to be compatible.

Programming the real time clock is

described in the software section.

• A breakout switch to enable program

analysis using the Z-100's enhanced Monitor

ROM utilities from the hand prompt or the

DEBUG utility.

• A prototype area for adding your own

options. One idea is to add a second

NVsRAM chip selected by means of a

toggle switch.

Theory of Operation

Main Schematic

Input Buffers

U1, 74LS245, provides buffering for the Data lines

(DO0 through DO7) from the S-100 bus to the

Interface board. U1 is enabled by the signal

/IO_Write.

U2, 74LS244, provides buffering for the Data lines

(DI0 through DI7) from the Interface board to the

S-100 bus. U2 is enabled by the signal /IO_Read.

Address Decoding

The board is uniquely decoded at address 0080h

through 008Fh by the Altera chip. S100 bus address

lines A00 through A15 are routed to the Altera chip

and these address lines are then decoded to only

allow addresses 0080h through 008Fh to affect card

operation.

This decoding could be changed but Altera chip

reprogramming would be required.

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Introduction 1
Theory of Operation 1